x86 mca: Not GP fault when guest write non 0s or 1s to MCA CTL MSRs.

x86 mca: Not GP fault when guest write non 0s or 1s to MCA CTL MSRs.

a) For Mci_CTL MSR, Guest can write any value to it. When read back,
it will be ANDed with the physical value. Some bit in physical value
can be 0, either because read-only in hardware (like masked by AMD's
Mci_CTL_MASK), or because Xen didn't enable it.
    If guest write some bit as 0, while that bit is 1 in host, we will
    not inject MCE corresponding that bank to guest, as we can't
    distinguish if the MCE is caused by the guest-cleared bit.

b) For MCG_CTL MSR, guest can write any value to it. When read back,
it will be ANDed with the physical value.
    If guest does not write all 1s. In mca_ctl_conflict(), we simply
    not inject any vMCE to guest if some bit is set in physical MSR
    while is cleared in guest 's vMCG_CTL MSR.

Signed-off-by: Jiang, Yunhong <yunhong.jiang@intel.com>